|Version 2 (modified by ffjeld, 10 years ago) (diff)|
What are CPU exceptions
CPU Exceptions is a low-level mechanism for invoking some exception handler, as defined by the X86 ISA architecture. The exception handler (i.e. an machine code-level function) can run at a different privilege level, with a different stack, etc. wrt. to the program that was running when the exception occurred.
Exceptions can be triggered either asynchronously by an interrupt (typically initiated by some peripheral hardware device) or synchronously as a side-effect of a CPU instruction (also called "software interrupts"). Synchronous exceptions can further be classified into explicit exceptions that are raised by some variant of the INT instruction, and implicit exceptions that are raised to signal some condition, such as division-by-zero or page-fault.
CPU exceptions vs. Common Lisp conditions
From a birds-eye perspective, it seems clear that certain implicit CPU exceptions must be mapped to corresponding Lisp-level conditions being signaled. For example, the division-by-zero CPU exception must trigger a division-by-zero error condition. (A conceivable but infeasible alternative would be that the compiler protects each division operation by explicitly testing the divisor for zero.)
The Movitz run-time also uses explicit CPU exceptions as a mechanism for triggering Lisp conditions. This mechanism is used primarily because it is (memory) space efficient: Only a two-byte instruction is required for raising an arbitrary CPU exception. However, the overhead (in terms of CPU cycles, say, in the hundreds) is not negligible, so this mechanism should only be used for situations that are truly exceptional.